According to foreign media reports, Google has kicked off R&D for its tenth-generation TPU and invited AMD to participate in part of the chip design, with potential collaboration spanning advanced packaging, CPU IP, and interconnect technologies. The new-generation TPU is expected to integrate CPU cores directly into the package for the first time, aiming to boost execution efficiency for AI inference tasks such as reinforcement learning and agent-based applications. While the ninth-generation TPU is still being developed with participation from Broadcom and MediaTek, the tenth-generation product is likely to feature specialized optimizations for agent and reinforcement learning scenarios.
This move comes against a backdrop of rapidly evolving AI workload structures. Beyond large model training, the share of agent reasoning and reinforcement learning tasks is climbing quickly. These workloads demand low-latency, high-concurrency small-scale inference — areas where general-purpose accelerators may not deliver the most efficient results. Google's decision to pursue specialized optimizations at the chip architecture level is essentially an early bet on where the next wave of computing power demand will emerge.
From a product cadence perspective, Google just launched its eighth-generation TPU at Cloud Next 2026 this year, and has already initiated tenth-generation R&D — a notably accelerated generational pace. The integration of CPU cores in the package and the advanced packaging partnership with AMD both point to the same direction: tightly coupling heterogeneous computing resources, bringing accelerators closer to dynamic inference scenarios such as agents and reinforcement learning, and reducing efficiency losses caused by cross-chip data transfers.
However, specialization also introduces new challenges. Agent-customized computing chips require deep coordination with software frameworks and scheduling systems — the more specialized the hardware, the more complex the ecosystem adaptation becomes. For enterprise users, computing power choices are becoming more diverse yet also more complex. How to achieve unified scheduling and elastic allocation across different chips will become a practical challenge in real-world deployment.
The shift toward agent-specific computing chips means the computing power supply for intelligent agent applications will become more granular and diversified. StarWar Cloud's continued investment in GPU computing platforms and compute scheduling is precisely aimed at helping enterprises achieve elastic allocation and unified scheduling in the new heterogeneous computing environment, ensuring that agent applications always have stable, efficient computing support.
Google's actions also reflect a broader industry transformation: from "whose chip trains large models fastest" to "whose chip runs agents more cost-effectively and stably." NVIDIA, AMD, and major cloud providers are all ramping up efforts around agent and inference optimization. The main battleground of computing power competition is shifting from training to inference and agent collaboration, which will profoundly reshape the future computing power market landscape.
The tenth-generation TPU is still in early-stage R&D, but the direction is already clear: computing power is moving from "general-purpose benchmarking" to "built for intelligent agents." Every specialized optimization by hardware vendors clears performance hurdles for large-scale multi-agent deployment — and signals that computing infrastructure is entering a new cycle of reconstruction centered around intelligent agents.