As AI large models grow exponentially in scale, the memory wall problem of traditional chip architectures has become a core obstacle to improving computing power, with the mismatch between computing demands and hardware development intensifying. The research team from Purdue University and the Georgia Institute of Technology has jointly proposed an innovative solution, marking a deep academic exploration of AI infrastructure. By integrating processing and memory units, this approach injects new momentum into AI industry trends. The von Neumann architecture, in use since 1945, suffers from inefficient data transfer due to its separation design, and the memory wall issue has become especially prominent in the era of large models. Over the past four years, the size of language models has surged by a factor of 5,000, while energy consumption has skyrocketed.
The study proposes CIM technology as a solution, embedding computing capabilities directly into the memory system—a potential new standard for next-generation chip design that significantly reduces data movement overhead. The core algorithm employs spiking neural networks (SNNs), whose efficiency gains stem from a spike-coding mechanism. Recent performance leaps in SNNs have addressed earlier shortcomings in speed and accuracy. The advantage of CIM lies in its architectural innovation, providing more efficient computing power support for AI large models while lowering energy consumption and improving processing efficiency. The application prospects are vast: under the trend of edge computing, this technology will drive the democratization of AI, enabling smart devices in healthcare, transportation, and drone sectors to achieve miniaturization, lower costs, and longer battery life, accelerating the adoption of intelligent applications.